1. Technical Field
The present invention relates in general to a computer system having a cache memory and write back buffers and, more particularly, to an apparatus and method for compressing cacheable data stored in one or more write back buffers.
2. Background of the Art
A computer system typically includes a processor and memory. When the processor can operate at a faster speed than the memory, then read/write operations to the memory can slow down the processor and degradate system performance. In order to enhance system performance, a cache memory and write back buffers are added to the computer system. A cache memory is a short-term, high-speed, high capacity computer memory. The processor simultaneously writes data to the cache memory and one write back buffer. Once the data is written to the cache memory and write back buffers, the processor may continue processing while the data is eventually written out to memory. At times, the processor may perform a number of write memory operations in a row such that all of the write back buffers become full. Should this happen the processor stalls until data can be written to memory. The number of write back buffers used is restricted due to a trade-off in space available for additional write back buffers versus the system performance gained with each additional buffer.
There have been attempts in the past to enhance system performance by providing a faster method of storing data in the memory. For example, one or more write back buffers have been used to minimize process stalls due to write operations. However, with this method, system utilization remains the same since write operations are merely delayed and not compressed. Further, in prior art systems, the write back buffer unit consisted of an address register to hold the address where the data was to be stored, byte enables to identify which parts of the data were valid for storing at the memory address, and a register or buffer to hold the data. However, in prior art devices it is still necessary to transfer all the bits of data to main memory even when some of the bits of data are no longer needed.
One example of a prior art attempt to enhance system performance is described in U.S. Pat. No. 4,742,446 entitled, "Computer System Using Cache Buffer Storage Unit and Independent Storage Buffer Device for Store Through Operation". This patent discloses an apparatus which enables the packing of sequential writes of sequential data for efficient transfer to main memory. However, it does not permit the packing of non-sequential writes for efficient transfer to main memory. Therefore, when there are several non-sequential writes to main memory, each is written independently thereby causing more write operations than needed, degradating system performance.
Accordingly, a need still exists for an approach which improves system performance by reducing the number of writes to main memory and the number of required write back buffers.